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Overview From the company that brought you the revolutionary Z80® comes the future of 16-bit processing - the ZNEO Z16F Series Flash Microcontroller. Zilog’s ZNEO Z16F is a powerful 16-bit CISC microcontroller that outperforms most RISC microcontrollers in its class. The ZNEO Z16F boasts a unique architecture that provides the power, punch, and performance of a 32-bit, with the code, current efficiency, and cost of a 16-bit. The ZNEO Z16F CPU boasts a highly optimized instruction set that achieves higher performance per clock cycle, with less code space and lower overhead than competing architectures.
This powerful, yet simple core with sixteen 32-bit general-purpose registers supports complex CISC addressing modes and a single-cycle instruction set that includes frame pointer support, multi-bit shift, and multi-register push/pop, as well as performance enhancing instructions such as Link and Unlink for lowering overhead. Powerful signed and unsigned math operations include 32x32 multiply and 64/32 divide operations.
A rich array of intelligent peripherals and analog features make this microcontroller suitable for a large number of applications, including security panels, industrial controls and motor control, including AC Induction and Brushless DC motors.
ZNEO Z16F Key Feature Summary: • 16-bit optimized Single-Cycle CISC core
• 128 KB of in-circuit programmable Flash memory
• Highly integrated Digital/Analog peripherals
- Operational Amplifier
- Analog Comparator
- Internal Precision Oscillator
- 4-Channel DMA Controller
- 12-bit PWM module
• Flexible communication interfaces, including two 9-bit UARTs with LIN & IrDA, I2C, ESPI
• 12-Channel, 10-bit ADC with a time tag that supports simultaneous conversions
ZNEO CPU Core Features: • Register-to-register-based architecture
• 20 MIPS throughput at 20 MHz
• 8-, 16-, and 32-bit ALU operations
• 16-bit internal and external bus widths
• Built-in 32 x 32 multiply operations
(signed and unsigned)
• Built-in 64 by 32 divide (unsigned)
• Compiler friendly instruction set | |
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