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| HCS08R 处理器 |
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部件型号 |
家族 |
制造商 |
内核变量 |
频率 |
Flash/ROM |
封装 |
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MC9S08RG60 |
HCS08AS |
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S08 |
8MHz |
59348 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RG32 |
HCS08AS |
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S08 |
8MHz |
32768 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RE8 |
HCS08AS |
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S08 |
8MHz |
8192 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RE16 |
HCS08AS |
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S08 |
8MHz |
16384 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RD8 |
HCS08AS |
 |
S08 |
8MHz |
8192 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RD60 |
HCS08AS |
 |
S08 |
8MHz |
59348 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RD32 |
HCS08AS |
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S08 |
8MHz |
32768 |
QFP32/44, SOIC28, DIP28 |
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MC9S08RD16 |
HCS08AS |
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S08 |
8MHz |
16384 |
QFP32/44, SOIC28, DIP28 |
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The MC9S08RC/RD/RE/RG are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in this family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types.
Features of the MC9S08RC/RD/RE/RG Family of devices
HCS08 CPU (Central Processor Unit)
- Object code fully upward-compatible with M68HC05 and M68HC08 Families
- HC08 instruction set with added BGND instruction
- Support for up to 32 interrupt/reset sources
- Power-saving modes: wait plus three stops
On-Chip Memory
- On-chip in-circuit programmable FLASH memory with block protection and security option
- On-chip random-access memory (RAM)
Oscillator (OSC)
- Low power oscillator capable of operating from crystal or resonator from 1 to 16 MHz
- 8 MHz internal bus frequency
Analog Comparator (ACMP1)
- On-chip analog comparator with internal reference (ACMP1)
- Full rail-to-rail supply operation
- Option to compare to a fixed internal bandgap reference voltage
Serial Communications Interface Module (SCI1)
- Full-duplex, standard non-return-to-zero (NRZ) format
- Double-buffered transmitter and receiver with separate enables
- Programmable 8-bit or 9-bit character length
- Programmable baud rates (13-bit modulo divider)
Serial Peripheral Interface Module (SPI1)
- Master or slave mode operation
- Full-duplex or single-wire bidirectional option
- Programmable transmit bit rate
- Double-buffered transmit and receive
- Serial clock phase and polarity options
- Slave select output
- Selectable MSB-first or LSB-first shifting
Timer/Pulse-Width Modulator (TPM1)
- 2-channel, 16-bit timer/pulse-width modulator (TPM1) module that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM
- Selectable input capture, output compare, and edge-aligned or center-aligned PWM capability on each channel
Keyboard Interrupt Ports (KBI1, KBI2)
- Providing 12 keyboard interrupts
- Eight with falling-edge/low-level plus four with selectable polarity
- KBI1 inputs can be configured for edge-only sensitivity or edge-and-level sensitivity
Carrier Modulator Timer (CMT)
- Dedicated infrared output (IRO) pin
- Drives IRO pin for remote control communications
- Can be disconnected from IRO pin and used as output compare timer
- IRO output pin has high-current sink capability
Development Support
- Background debugging system (see also the Development Support chapter)
- Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
- Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints.
Port Pins
- Eight high-current pins (limited by maximum package dissipation)
- Software selectable pullups on ports when used as input. Selection is on an individual port bit basis. During output mode, pullups are disengaged.
- 39 general-purpose input/output (I/O) pins, depending on package selection
Package Options
- 28-pin plastic dual in-line package (PDIP)
- 28-pin small outline integrated circuit (SOIC)
- 32-pin low-profile quad flat package (LQFP)
- 44-pin low-profile quad flat package (LQFP)
- 48-pin quad flat package (QFN)
System Protection
- Optional computer operating properly (COP) reset
- Low-voltage detection with reset or interrupt
- Illegal opcode detection with reset
- Illegal address detection with reset (some devices don’t have illegal addresses)
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