MPC8360E Features

> e300 core operating from 266 MHz to 667 MHz

•  32-bit, high-performance superscalar core
•  1,261 MIPS at 667 MHz; 503 MIPS at 266 MHz
•  Double-precision floating point, integer, load/store, system register branch processor units and 32 KB data and 32 KB instruction cache with line-locking support

> QUICC Engine initially operating up to 500 MHz

•  Two 32-bit RISC controllers for flexible support of the communications peripherals
•  Eight unified communication controllers (UCCs) supporting the following protocols and interfaces:
  •  10/100/1000 Mbps Ethernet
  •  ATM SAR supporting AAL5, AAL2, AAL1,AAL0, TM 4.0 CBR,VBR, UBR traffic types, up to 64KB external connections
  •  Inverse multiplexing for ATM (IMA)
  •  POS up to 622 Mbps
  •  Transparent
  •  HDLC
  •  Multilink, multiclass PPP
  •  HDLC bus
  •  UART
  •  BISYNC
•  One multichannel communication controller (MCC) supporting
  •  256 channels with up to eight TDMs
  •  Transparent and HDLC mode per channel
  •  Support for Signaling System Number 7 (SS7)
  •  Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces
•  Two UTOPIA/POS interfaces supporting up to 128 multi-PHY each
•  Two serial peripheral interface (SPI)
•  Eight TDM interfaces (T1/E1)
  •  Aggregate bandwidth of 64 kbps and 256 channels
  •  Maximum of 16 Mbps and 256 channels on a single TDM link
  •  2,048 bytes of SI RAM (1,024 entries)
  •  Eight programmable strobes
  •  Bit or byte resolution
  •  Independent transmit and receive routing, frame synchronization
  •  Supports T1, CEPT, T1/E1, T3/E3, pulse-code modulation highway, ISDNprimary/basic rate, Freescale interchip digital link (IDL) and user-defined TDM serial interfaces
•  Sixteen independent baud rate generators
•  Four independent 16-bit timers that can be interconnected as two 32-bit timers
•  Two SPI ports that can be configured as an Ethernet management port for management data input/output (MDIO), while the other can be configured for low-cost serial peripherals; the SPI also has a CPU mode that can be configured by the CPU and not through the QUICC Engine

> USB interface (USB 2.0 full-/low-speed compatible)

> DDR memory controller

•  Programmable timing supporting both DDR1 and DDR2 SDRAM
•  2 x 32-bit or 1 x 64-bit data interface; up to 333 MHz data rate
•  Four banks of memory, each up to 1 GB
•  Full ECC support

> PCI interface

•  One 32-bit PCI 2.2 bus controller (3.3V I/O; up to 66 MHz)

> Integrated security (MPC8360E and MPC8358E only)

•  Public key execution (RSA and Diffie-Hellman)
•  Data encryption standard execution (DES and 3DES)
•  Advanced encryption standard (AES) execution
•  ARC-4 execution (RC4-compatible algorithm)
•  Message digest execution (SHA, MD5, HMAC)
•  Random number generation (RNG)

> Local bus controller

•  Multiplexed 32-bit address and data operating up to 133 MHz
•  32-, 16- and 8-bit port sizes controlled by on-chip memory controller

> Dual UART (DUART)

> Dual I2C interfaces (master or slave mode)

> Four-channel DMA controller

> General-purpose parallel I/O

> IEEE 1149.1 JTAG test access port

> Package option: 37.5 mm x 37.5 mm 740 TBGA

> Process technology: 130 nm CMOS

> Voltage: 1.2V core voltage with 3.3V and 2.5V I/O